Ser Hou Kuang & Sean Murphy Granted US Patent #7162706 B2 for “Method for Analyzing and Validating Clock Integration Properties in Circuit Systems” on January 9, 2007.
Abstract: A method for analyzing and validating clock integration properties in a circuit design is disclosed. A database of timing points that are clocked cell elements of the circuit design is generated. Next, a timing point frame showing the interaction of the clocked cell elements and the non-clocked cell elements is generated. The timing point frame graphically shows the timing network properties for the cell elements of the circuit design. A clock analysis view can be generated from the timing point frame for selected timing points. In this respect, the timing point frame shows timing points that meet a prescribed criteria (e.g., same clock domain). Therefore, the clock analysis view provides a graphical representation of timing and clock interactions for the circuit design.
Here are excerpts from the PicoCraft datasheet for it’s initial offering
Clock Domain Profiler and Analysis tool that leverages your existing Static Timing setup and Library, to rapidly identify likely Synchronization Errors in the final tape-out netlist for high clock-count multi-million gate SOC designs.
- Uncover Asynchronous CDC Errors PrimeTime Ignores
- High Capacity: Fast Turnaround of Full Chip Analyses
- Exhaustive Root-Cause Analysis for all Modes
This is a challenge related to but distinct from detailed timing analysis, complicated by several design trends that we believe will continue to accelerate over the next two to three process nodes:
- Increasingly complex power management schemes are proliferating the number of distinct operating modes that need to be analyzed.
- Higher levels of integration are increasing the number of distinct interfaces, each with their own on chip clocking and synchronization requirement.
- Clock trees are consuming a higher fraction of chip logic and require separate analysis that is aware of physical implementation and on chip variation effects.
Traditional static timing tool development teams at remain focused on calculating detailed timing that is highly correlated with Spice. New entrants are relying either on formal methods that work from pre-layout RTL but lack the capacity for full chip analysis or structural pattern recognition techniques that require naming conventions or a distinct set of cell models to work. GPP is unique in leveraging existing static timing models to build high level clock interaction representations from the physical implementation of a full chip.
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