Tim Lombard Launches PCBevo, a Unique Analysis Tool for PCB Layout

By | 2019-08-15T20:46:43+00:00 August 12th, 2019|EDA, Founder Story, skmurphy|0 Comments

An interview with Tim Lombard on a tool he has developed called PCBevo. PCBevo helps design engineers and layout designers track the co-evolution of the design specification and the layout of a Printed Circuit Board (PCB).

Tim Lombard Launches PCBevo, a Unique Analysis Tool for PCB Layout

Tim Lombard is the founder and managing director of PCBEvo. He spent more than 25 years at Cisco Systems as an ECAD application engineer, ECAD manager, EDA tools manager, and technology lead in operations. He brings six years of experience programming in Python and using it for data analysis to his first product startup.

I hired Tim in 1991 to drive Cisco’s PCB design efforts, and we have stayed in touch ever since. He is working on a very interesting software tool, PCBevo, that builds on his experience managing PCB layout groups at Cisco and his previous work running a PCB design service bureau. PCBevo  is designed to track the stream of design changes and PCB layout edits that occur during the transition from preliminary design netlist to finished layoff ready for fabrication and assembly. It helps the design engineer(s) and the layout team–and their respective chains of command–maintain a shared situational awareness on the progress to date and  status of a design,  and the impact any design changes that have been made.

It’s a challenging problem area because the layout designer typically has to start from an incomplete specification to help the design team get a feel for the final board size and other layout constraints. The layout designer will try to work on those parts of the design that are the most complete while the engineer works to finish the design, making changes in response to new requirements, design validation and verification issues, and periodic flashes of insight as to how to improve performance or save space. The layout may also need to rip up and retry the layout for a portion of the board, either because the current approach did not work or design changes have rendered the old plan at last partially obsolete. Lombard developed PCBevo to help engineers and layout designers maintain a better shared understanding of the state of the design and the impact of recent or potential changes.

Q: Can you talk a little bit about your background

Tim Lombard, founder of PCBevoIn answering that question, It’s amusing to me that you were my hiring manager when I joined Cisco in the early ’90s. The internet was in its infancy, and Cisco was to experience explosive growth. The count of initiatives requiring hardware and PCBs was staggering. We needed to upgrade to modern tools and develop design flow methods that leveraged our libraries. It seemed that by the time Cisco formally committed to an initiative, the initiative was already late.

Q: I always felt that projects existed in one of two starts at an executive staff level: “probably not a good idea” and “late.” It made for a nice two column Kanban board. You held a variety of roles at Cisco in 25 years there.

I had a variety of roles at Cisco but they were all engineering related. I worked as Application Engineer where I developed methodologies for the PCB design process. At one point I was an ECAD manager with a large team of PCB Layout Engineers. I spent time ECAD Tools manager where I worked on standardizing the board-flow method including management of high-speed rules. My last roles was a Technical Lead of Operations where my focus was collecting and organizing engineering information for analysis.

PCBevo logoQ: You had some specific experiences at Cisco that led you to create an internal tool to track design status on a netlist change by netlist change basis, can you give us the “origin story” for PCB Evo?

It was about 2001 when Cisco started to develop “HFR” or what is now known as CRS-1. This system was based on a set of large (over 1000 pins) internally developed ASICs, a large midplane design, with a host of large and highly constrained (e.g. differential pairs, relative delay rules, max vias on a line, noisy clock-lines, etc.) line cards and PLIMs.

We had to prototype at least 42 different PCBs. I had just joined the HFR team as the manager for their PCB layout team. A key activity for my job was to report status to the Director of Hardware for the HFR project. This director, Doug Knight, was under tremendous pressure to deliver the PCBs on time with first article ASICs. He was emphatic about wanting to know the complete and up-to-date status for all of PCB layouts that I was supervising. My initial attempts at providing progress reports required a lot of tedious effort to deliver information that quickly went stale.

With the help of some programmers, we cobbled together a basic system in Perl, Excel, and MySQL on a web-server. This system provided stakeholders like Doug with basic status information that was updated daily. Fast-forward to about 2010 when the Hardware Director for a different product line phoned me in a panic. He was worried that one of his large and complex line cards was not going to meet the schedule agreement for fab-out. I was away from my desk, but over the phone, I was able to direct him to the web-tool for PCB status and then over to the project in question. I asked him to look at the number of connections (“the blue line”) and tell me if it was smooth or jumping up-and-down. He said it was jumping up.

I explained that that blue line was the number of connections for this project. It can only change with a change in the netlist from the Hardware Engineers on the project. I went on to explain that this design was partitioned into four sections with four of our best PCB layout engineers working each section. To read in a netlist change; the partitions had to be re-assembled. The process of re-assembling the partitions to read in a new netlist on a project of this size takes about 3-4 hours. I could sense his appreciation for this information. He thanked me for explaining and told me to expect fewer changes in the final days before the scheduled target. I later heard that he called his HW engineers into a meeting and shared what happened in our phone call. The project was a bit late but successfully shipped to fabrication for a prototype.

Sometime after this exchange, It occurred to me that having accurate, up-to-date data to inform stakeholders instills confidence. Confidence for the PCB Layout managers to make a defensible request for schedule changes and confidence for the stakeholder that his PCB layout team is making measurable progress on essential projects.

Q: After you left Cisco you started from scratch and crafted a cloud version, where does that stand today?

PCBevo view of agreement between engineer and layout designerIn my last three years at Cisco, I transferred to an Engineering Services Operations role where I learned to write scripts for data collection and analysis. After Cisco, I thought to build on the idea of tracking PCB projects using my new data science skills. The new version not only graphs the progress of a project over time, but it also records what I like to call “the agreement.” The agreement consists of three elements, scope, schedule and budget. With the agreement in place, more insights can be gleaned from a project like “Days Late” or “Dollars Over Budget.”

I have demonstrated the minimal viable product version  of the MVP to several industry experts. Their reactions to the demos have been consistently positive.

Q: What’s been the most surprising development so far?

The journey to create a production quality cloud application has been a source of many surprises. One area that comes to mind is the feedback from experts who have seen a demo of the tool. One expert asked if the data collected could provide insights on the workload for the PCB Layout team. His theory is that this information could inform the decision to add or reduce staff.

Q: You are giving a talk in September at the PCB Conference in San Jose?

It’s entitled “Analytic Approach to Project Management of PCB Designs.” It’s Session 40 at the PCB West 2019 conference, scheduled for Wed-Sep-11 1:30-3:30. It’s not one of the open session, you have to buy a full conference ticket to be able to attend. The key topic I want to explore is:

PCB Layout is a complex and often fast-moving transformation of a design concept into the real fabrication spec for a prototype. Tracking PCB Layout progress can provide powerful insights and inform decisions for meeting new product goals. Without adjustments to the overall project plan, schedule slips in the PCB Layout phase can adversely affect the overall project schedule. Late product delivery is expensive.

My goal is for a discussion that explores how data collected from today’s PCB Layout tools can be analyzed to create powerful insights. In particular:

  • How key measures can be tracked as they progress toward 100%
  • How can data analysis provide early detection and impact reporting should the scope change?
  • How can data analysis provide can justify a new agreement for more time or money.
  • How can one start collecting data on PCB Layout progress to analyze?

I am looking forward to a lively discussion with a number of experienced PCB designers who attend PCB West.

Q: Tim, thanks for your time.

SKMurphy Take

Tim has a long and successful track record applying automation and analytics early to PCB design problems that were initially poorly understood. Although ASIC design tends to get most of the attention because it has grown dramatically more complex over the last 30 years, with a large chip transitioning from thousands of gates to millions of gates, PCB design has also become much more challenging as well. Tim recognized very early that the design specification for a PCB was going to contains tens of thousands of constraint properties to help manage the routing of differential pairs, relative delay in buses,  clock noise, signal cross-talk, thermal constraints, mechanical constraints such as component height restrictions, and many more. A PCB design specification is 70-90% constraints today: Tim developed tools two decades ago that anticipated that reality and made it manageable by compressing the constraint descriptions to 10-20% of the design.

The other reality is that time to market pressure have rendered the old “relay race” model obsolete: layout cannot wait until the design is completely frozen to start work. Worse, the layout has a much higher impact on performance so the engineer needs to see preliminary and evolving layout results to get a more accurate picture of likely circuit performance to be able to freeze the design. There is also a non-linear aspect to design completion, it’s not just that the first 90% of the nets take 90% of the time and the last 10% take the other 90%, the last 1% of the nets can take as long as the first 99% in very complex and high performance designs. Coming up with better ways to track progress and estimate final completion dates becomes much more valuable as a result. I think some of the analytic techniques he has developed for PCBevo are also applicable to other complex multi-disciplinary projects.

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