“As the founder of a small EDA startup, I have found Sean to be a valuable strategic advisor. He helped with the business and product strategies and contributed to our first patent as a co-author. He developed marketing materials and our early sales pitch. He was instrumental in securing our first customers.”
Ser Hou Kunang CEO, PicoCraft
About PicoCraft
Incorporated in 1998, PicoCraft initially provided design consulting services. As we observed the same challenges on different chips that current tools did not address, they developed GPP, a general purpose profiling tool for mapping clock domains and managing asynchronous clock domain crossing signals.
Because either PrimeTime® or EinstimerTM was already in use for detailed path delay analysis, GPP was designed to complement and extend existing static timing tools. In particular:
- GPP works directly from PrimeTime configuration files.
- GPP offers a fast full chip CDC analysis.
- GPP can validate each mode in the case analysis set and provide a profile of the direction and magnitude of clock domain interactions.
- In addition to basic clock propagation integrity checks, GPP automates root cause analysis for missing control signals.
A new EDA market segment is emerging around the need to analyze and manage clock interactions in high performance SoC’s. This is a challenge related to but distinct from detailed timing analysis, complicated by several design trends that we believe will continue to accelerate over the next two to three process nodes:
- Increasingly complex power management schemes are proliferating the number of distinct operating modes that need to be analyzed.
- Higher levels of integration are increasing the number of distinct interfaces, each with their own on chip clocking and synchronization requirement.
- Clock trees are consuming a higher fraction of chip logic and require separate analysis that is aware of physical implementation and on chip variation effects.
Traditional static timing tool development teams at remain focused on calculating detailed timing that is highly correlated with Spice. New entrants are relying either on formal methods that work from pre-layout RTL but lack the capacity for full chip analysis or structural pattern recognition techniques that require naming conventions or a distinct set of cell models to work. GPP is unique in leveraging existing static timing models to build high level clock interaction representations from the physical implementation of a full chip.