Kurt Keutzer on Engineering Entrepreneurship & EDA

Highlights from an interview with Kurt Keutzer as part of the 2010 Design Automation Conference.  He uses Foster’s S-curve from “Innovation: The Attacker’s Advantage” to offer perspective on EDA.

Kurt Keutzer on Engineering Entrepreneurship & EDA

Kurt Keutzer was interviewed June 8, 2010 on the DAC website and he had a number of interesting things to say about engineering and entrepreneurship.  What follows are some excerpts but it’s worth reading the entire interview. I have added several hyperlinks for context.

Career advice he gives his students:

  • I think that every engineer needs to realize today that fundamentally they are a corporation of size 1. There’s no lifetime employment and a career is no longer a simple matter of riding the escalator in a big company. Individual entrepreneurship is a requirement, not an option.
  • Every engineer needs to know how to assess the value of the technology they are working on. They need to know the difference between a technology, a product, and a market-maker.
  • To do this they need to know how to identify a market, size it, and segment it. They need to understand the difference between technological advance and creating customer value, and that customers will pay for value and not, per se, technology.
  • To understand this they have to be able to take a step back from technology and see the world through the eyes of the customer.
  • In terms of career directions my advice is go where the growth is. In Foster’s classic S-curve [from “Innovation; The Attacker’s Advantage], areas of technology tend to go through long fallow periods in which not much progress is made. Then there’s a period of explosive growth. Then there’s another long fallow period. You want to be right around the inflection point of explosive growth. Putting a lot of effort in an area, either too early or too late, will not yield results comparable to what even a modest amount of effort will yield when invested at the right time.

How would he  apply technology S curve analysis to EDA?

  • I wish I knew. EDA seems to be experiencing one of its longest plateaus in its history.
  • EDA and the semiconductor industry seem to be in what could be called a “non-virtuous cycle” (i.e., a vicious cycle). New generations of EDA tools are not improving individual productivity very dramatically even as Moore’s Law continues. So the cost of building chips, of which the principal component is human capital, has risen exponentially. This high cost has led to fewer and fewer leading-edge designs each year. This means that EDA companies must charge the leading-edge customers more and more to keep their revenues up. This means the cost of leading-edge design increases further. It’s a downward spiral.
  • FPGA suppliers have created another “non-virtuous cycle.” FPGA makers seek to control their own destiny by giving away tools for free. There are two problems with this.
    1. The tools FPGA vendors give away aren’t very good so designers aren’t very happy  with the flows. For example, I can’t get my students to use FPGAs anymore if they have the alternative to use software-programmable standard parts.
    2. Because the tools are free, third-party tool companies can’t get a foothold to provide better tools. I believe that poor tools and design flows is one of the biggest inhibitors to the growth the FPGA industry.

Update June-23-2010: Paul McCllelan offers this perspective on what’s holding EDA back in his “DAC 2010 Retrospective

EDA is still somewhat stuck in an outmoded style of design that assumes the chips are designed from scratch and then someone writes some software to run on them. In fact much of the software already exists: software generations are 10 times as long as chip generations, and chip design is increasingly about IP assembly rather than efficient design from scratch. I continue to believe that this block-level is an interesting choke point, with the potential to generate a virtual platform for the software developers and testers, and the potential to turn the design rapidly into an FPGA or SoC. But the tools don’t yet exist.

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