ASIC Design Starts Dropping: Implications for EDA

I attended a very thought provoking talk tonight on “Factors Influencing IC Design Starts and Future Revenues” by Bryan Lewis and John Barber of Gartner at the Santa Clara Valley Chapter of the IEEE Components, Packaging & Manufacturing Technology Society. Bryan and John declined to make their slides available but I was able to crib this chart from an EE Times article “Sockets scant for costly ASICs

2000 2005 2006 2007 2008
7,749 3,623 3,391 3,196 3,048

Chip volume and complexity combine to increase total revenues but the design start trend has clear implications for an EDA industry that in the 80’s and 90’s saw ASICs (gate array and standard cells) as key drivers. The other interesting trend is that process lifetimes are elongating considerably. The need to move to a new process was another strong driver in the 90’s as deep submicron and then very deep submicron processes required entirely new back end tool sets to accurately model their complexities and constraints. This is a trend that has been underway for more than a decade as the EE Times article points out

Back in the mid-1990s, any given year saw a total of some 10,000 ASIC design starts, according to iSuppli. A design start is equal to a unique tapeout, but the IC may or may not go into production, Gartner’s Lewis said.

It would seem that the near term EDA opportunities may have more to do with complexity management as complexity continues to increase, and intelligent management and recycling of legacy design data.

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