I have followed Herb Reiter‘s consulting career over the last five years or so: there aren’t very many business development consultants who work with EDA firms, fewer who have the mix of semiconductor and design background that Herb accumulated on the way to honing his business development expertise. He is personable, methodical, and always interested in talking with new start-ups. He gives good advice informed by a perspective on both industry and technology trends. When he met with PicoCraft a while back he mentioned that he had been part of the team at Synopsys that helped to establish PrimeTime as a de facto standard for STA (Static Timing Analysis), building on experience he had gained doing the same for Motive at Viewlogic before they were acquired by Synopsys. I caught up with him recently and asked him to tell the story of PrimeTime’s early customer development and lessons it may hold for other EDA companies, especially start-ups. What follows is an edited (and hyperlinked, good blogging is good linking) transcript of our conversation.
Q: Can you give me a brief bio and some background on the events that allowed you to establish static timing analysis as a viable new tool in the ASIC design flow and PrimeTime as a key player in that market?
I spent almost 20 year in semiconductors, I have seen the consequences of insufficient design tools. For example, in the early to mid 80′s I was part of National Semiconductor‘s plan to bring their impressive portfolio of micro controllers, communication chips, and other ASSPs as mega-cells into the rapidly growing ASIC world. A lack of good tools was the primary reason for this failed attempt.
When I joined VLSI Technology in 1989, VLSI had the best cell-based tools and flows. Their design centers were world-class, working with leading edge IC design teams at very successful companies. I got a close up view of the challenges the development of ASIC core technology represented. As VLSI’s lead in cell-based design methodologies waned, revenues and profits declined and eventually Philips acquired VLSI. After VLSI I joined Viewlogic. After I had been working there for a year, successfully encouraging many ASIC vendors to qualify Motive STA and VCS gate-level simulation as sign-off methodologies. Then Synopsys offered around $400M to Viewlogic’s shareholders and we merged with our former competitor.
Q: It’s rare that a larger EDA firm is able to develop and launch a new product in a new area. As you said, you were part of the Viewlogic acquisition at Synopsys. How did you build internal support to enable PrimeTime to achieve not just traction in the market, but ultimately dominant market share?
At Viewlogic we had been winning accounts with Motive against Synopsys/PrimeTime at Viewlogic. When I “changed sides” many members of the PrimeTime team were interested in our approach. The first thing that I did for Motive and then for PrimeTime, was to narrow our focus from dozens of potential partners to the top dozen technology leaders. Both at Viewlogic and Synopsys my team used the same basic formula: We worked hard to understand our partners’ requirements, developed trust relationships with a dozen ASIC semiconductor vendors. This allowed us to make Motive and then PrimeTime an integral part of their ASIC design flows and the key to timing sign-off.
Just like my semiconductor partners, I had engineering sites all over the world, I wanted my people to be as close to these partners as possible. One of my engineering experts even worked at TSMC in Taiwan, and was instrumental in implementing Dr. Ping Yang’s vision of TSMC’s reference flow number one.
We also waived the PrimeTime training fees for the ASIC Design Centers of our partners. Synopsys’ product group gladly covered the training department’s exploding expenses and was rewarded with a flood of PrimeTime bookings from these Design Centers and their many ASIC customers. Just like TSMC‘s first and second reference flows–which were dominated by Synopsys tools–increased Synopsys revenues at fabless IC vendors, these ASIC Design Center seminars did the same at our big partners and their ASIC customers. Most of the smaller ASIC vendors adopted PrimeTime quickly, after seeing its benefits giving their larger rivals a competitive advantage, and a de-facto Timing sign-off standard was established in about two years.
Q: What were a couple of lessons learned?
Introducing new EDA design tools is a lengthy and difficult process. Gate-level timing simulation was the proven and trusted methodology for timing verification through the 0.35 micron process node. But at 0.25 micron chip complexities and clock speeds increased the challenge of chip level timing closure, 0.18 micron was even more difficult, such that simulation run times approached eternity. Mask and re-spins costs, coupled with the economic impact of being late to market meant that an exhaustive method that guaranteed timing closure was urgently needed. PrimeTime’s static timing analysis offered a comparatively very fast way to do exhaustive timing verification and the product group as well as my team offered excellent support during this transition.
It’s important to note that static timing analysis had been around for more than a decade, Motive had originally been used for board level design. When my ASIC Vendor team at Viewlogic together with the Motive developers introduced it to the semiconductor vendors, we learned a key lesson: People were not willing to abandon a methodology that is working until it seriously hit their pocket book. Eternal runtimes of 0.18 micron chips and expensive re-spins because dynamic simulation is not exhaustive, helped us win STA converts.
Q: How big an issue was library management for the ASIC vendors?
Huge, ASIC vendors were at first reluctant to take on creating and supporting yet another library. One common complaint that I heard many times from ASIC vendors: supporting different libraries for different process technologies was a never ending effort. This huge effort got multiplied by the number of tools that relied on accurate libraries and, to make matters even worse, required a complete update and re-verification, whenever a new tool revision was introduced. I knew that we had to make it much easier for our customers to manage these libraries.
Q: When you talk about AEware (scripts written by Applications Engineers to supplement and extend the base product?
Already at VLSI I have seen our design centers developing a lot of what you call AEware, primarily to overcome tools deficiencies or extend the life of a proven tool. My Silicon Vendor Program team at Synopsys worked very closely with the strong corporate CAD groups at our partners to temporarily give Synopsys tools important capabilities for chip design within existing flows and to demonstrate to the Synopsys product groups the importance of such features–with remarkable success. The product groups, especially the PrimeTime team, adopted many of these scripts and made them integral and professionally supported parts of the next tools releases.
Q: Can you talk about how this experience led you to form EDA 2 ASIC Consulting and what your business is today?
In my role managing the Synopsys Silicon Vendor Program team I really enjoyed being a bridge between the powerful ASIC industry and the innovative EDA industry. I saw PrimeTime, VCS, TetraMax, Physical Compiler and other Synopsys tools getting accepted widely and really making a big difference for our highly interdependent industries. When I started my own firm in 2002 I wanted to replicate my dream-job: Being a bridge between these two industries and bringing to my friends in the semiconductor industry innovative EDA solutions, now primarily from smaller EDA vendors. In the 7 years of managing my own firm I have been able to make a number of contributions to the semiconductor industry. But I still look back at the work I did at Synopsys. Together with the product group and the training department, we laid the groundwork for PrimeTime’s market dominance as a lasting contribution. PrimeTime is still at 87% market share today, almost ten years later, according to Gary Smith EDA.